The 4th HPCA Workshop on
Accelerator Architecture in
Computational Biology and Bioinformatics

June 18th, 2022

In conjunction with 49th IEEE International Symposium on Computer Architecture

New York City, New York, USA

Workshop website

Submission link

Submission Deadline - April 30, 2022, EoD AoE
Notifications - May 15, 2022


Over the last decade, the advent of high-throughput sequencing techniques brought an exponential growth in sequenced data. At the same time, the single-thread performance continued to improve by only a few percent point annually. The growing gap between the performance demand to performance supply became a significant challenge in the path to scientific discovery. The computational bottleneck of genome analysis pipelines became even more apparent during the ongoing Covid-19 pandemic, where fast and reliable virus detection and classification tools have been critical for the worldwide genomic surveillance system.

The gap between the performance of a conventional computer architecture and the biological data processing requirements is growing. For example, assembling a human genome from 3rd generation sequenced data may require hundreds of CPU hours. Hence, computational biology and bioinformatics will have to rely on hardware accelerators to allow processing to keep up with the exploding amount of sequenced data.

In a typical application, the dominant portion of the runtime is spent in a small number of computational kernels, making it an excellent target for hardware acceleration. The combination of increasingly large datasets and high performance computing requirements make computational biology a prime candidate to benefit from accelerator architecture research. Potential directions include 3D integration, near-data processing, in-data processing and reconfigurable architectures.

This workshop will focus on architecture and design of hardware accelerators for computational biology and bioinformatics problems. We plan to present and discuss a variety of acceleration techniques, accelerator architectures and their implications on the development of computational biology. This year, we plan to extend the industry angle, by providing a keynote and invited talks from leading industry research specialists.

List of Topics

This workshop focuses on architecture and design of hardware and software accelerators for computational biology and bioinformatics problems.

Topics of interest include, but are not limited to the following:
  • Hardware and software algorithms/applications in the fields of computational biology, such as (but not limited to)
    • Bioinformatics
    • Genomics
    • Proteomics
    • Protein structure prediction
    • Covid-19 pandemic
  • Bioinformatics and computational biology accelerator architecture and design based on (but not limited to):
    • 3D memory-logic stack
    • Near-data (in-memory) processing
    • In-data processing
    • FPGAs
    • Reconfigurable architectures
  • Emerging memory technologies and their impact on bioinformatics and computational biology
  • Impact of bioinformatics and biology applications on computer architecture research
  • Bioinformatics and computational biology-inspired hardware/software trade-offs


9:00 - 9:10 Opening Remarks

9:10 - 10:00 Onur Mutlu
"Accelerating Genome Analysis" (slides)
10:00 - 10:25 Yuhao Fang, Aman Sinha and Bo-Cheng Lai
"REAL-GSM : Re-programmable Engines for Acceleration on LPDDR4x-based Stacked DRAM to support Genomic String Matching"
10:25 - 10:40 Coffee break

10:40 - 11:05 Elena Espinosa, Ivan Fernandez, Rafael Larrosa Jiménez and Oscar Plata
"Whole-Genome Assembly: An Experimental Study of Computational Costs and Architectural Opportunities"
11:05 - 11:30 Alireza Mohammadidoost, Kyle Smith and Yatish Turakhia
"GPU Acceleration of Pairwise Sequence Alignment Using Wavefront Skipping" (slides)
11:30 - 11:55 Damla Senol Cali, Saugata Ghose and Onur Mutlu
"Accelerating Genome Sequence Analysis via Efficient Hardware/Algorithm Co-Design" (slides)

11:55 - 13:00 Lunch

13:00 - 13:50 Tajana Šimunić Rosing
"Accelerating bioinformatics workloads"
13:50 - 14:15 Miquel Moreto and Santiago Marco-Sola
"Accelerating the Wavefront Alignment Algorithm on CPUs, GPUs and FPGAs" (slides)
14:15 - 14:40 Nika Mansouri Ghiasi, Jisung Park, Harun Mustafa, Jeremie Kim, Ataberk Olgun, Arvid Gollwitzer, Damla Senol Cali, Can Firtina, Haiyu Mao, Nour Almadhoun Alserr, Rachata Ausavarungnirun, Nandita Vijaykumar, Mohammed Alser and Onur Mutlu
"GenStore: A High-Performance In-Storage Processing System for Genome Sequence Analysis"

14:40 - 14:50 Coffee break

14:50 - 15:40 Lisa Wu Wills
Balancing Specificity with Flexibility: How to Accelerate Genomic Analytics with a Composable Framework
15:40 - 16:05 Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits
"Hamming Distance vs. Edit Distance for Approximate Associative Genomic Processing"
16:05 - 16:30 Zheming Jin
"Performance Portability of Epistasis Detection using SYCL on a GPU"
16:30 - 16:40 Closing remarks

Keynote Speakers

  • Tajana Rosing

    Professor of Computer Science and Engineering, Director of System Energy Efficiency Lab, University of California, San Diego

    Short Bio: Tajana Šimunić Rosing is a Full Professor, a holder of the Fratamico Endowed Chair, ACM & IEEE Fellow, and a director of System Energy Efficiency Lab at UCSD. Her research interests are in energy efficient computing, computer architecture, distributed and embedded systems. She is leading a number of projects, including efforts funded by DARPA/SRC JUMP CRISP program, with focus on design of accelerators for analysis of big data including machine learning, image/video processing and bioinformatics; DARPA, NSF and SRC funded projects on Hyperdimensional Computing, SRC funded project acceleration of 3rd generation Fully Homomorphic Encryption, and NSF AI TILOS center projects on federated learning and AI-based chip design. She recently headed the effort on SmartCities that was a part of DARPA and industry funded TerraSwarm center. Tajana led the energy efficient datacenters theme in MuSyC center, and a number of large projects funded by both industry and government focused on power and thermal management. From 1998 until 2005 she was a full time research scientist at HP Labs while also leading research efforts at Stanford University. She finished her PhD in EE in 2001 at Stanford, concurrently with finishing her Masters in Engineering Management. Her PhD topic was dynamic management of power consumption. Prior to pursuing the PhD, she worked as a senior design engineer at Intel Corporation.

  • Onur Mutlu

    Professor of Computer Science, ETH Zurich and CMU

    Short Bio: Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, hardware security, and bioinformatics. A variety of techniques he, along with his group and collaborators, has invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received the Intel Outstanding Researcher Award, IEEE High Performance Computer Architecture Test of Time Award, the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, ACM SIGARCH Maurice Wilkes Award, the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, US National Science Foundation CAREER Award, Carnegie Mellon University Ladd Research Award, faculty partnership awards from various companies, and a healthy number of best paper or "Top Pick" paper recognitions at various computer systems, architecture, and security venues. He is an ACM Fellow "for contributions to computer architecture research, especially in memory systems", IEEE Fellow for "contributions to computer architecture research and practice", and an elected member of the Academy of Europe (Academia Europaea). His computer architecture and digital logic design course lectures and materials are freely available on YouTube, and his research group makes a wide variety of software and hardware artifacts freely available online For more information, please see his webpage at

  • Lisa Wu Wills

    Assistant Professor of Computer Science, Duke University

    Short Bio: Lisa Wu Wills is the Clare Boothe Luce Assistant Professor of Computer Science and ECE at Duke University. Prior to Duke, she was a postdoctoral researcher at the University of California, Berkeley and a research scientist at Intel Labs. Her research interests include computer architecture and microarchitecture, hardware acceleration, hardware-software co-design, emerging applications in big data such as database and graph analytics, healthcare such as genomics analytics, and artificial intelligence such as natural language processing for drug discovery. Wills has a PhD in computer science from Columbia University, a MS in computer science and engineering from the University of Michigan, Ann Arbor, and a BS in computer engineering from the University of Illinois, Urbana-Champaign. She has received an NSF CAREER award, three IEEE Micro Top Picks, and a MICRO best paper award.

Workshop Organizers

Leonid Yavits

Bar Ilan University

Short bio: Leonid Yavits is with Bar Ilan University, Israel. He received his MSc and PhD in Electrical Engineering from the Technion. After graduating, he co-founded VisionTech where he co-designed the world’s first single chip MPEG2 codec. Following VisionTech’s acquisition by Broadcom, he managed Broadcom Israel R&D and co-developed a number of video compression products. Later Leonid co-founded Horizon Semiconductors where he co-designed a Set Top Box-on-chip for cable and satellite TV. Leonid’s research interests include non von Neumann computer architectures, processing in memory, and domain specific accelerators. Leonid's research work has earned several awards; among them: IEEE Computer Architecture Letter Journal Best Paper Awards for 2015 and 2017 and best poster award at ICS High Performance Conference 2017.

Yatish Turakhia

University of California, San Diego

Short bio: Yatish Turakhia is assistant professor of Electrical and Computer Engineering (ECE) at UCSD. He was previously a postdoctoral scholar at the Genomics Institute at UC Santa Cruz and received his PhD student in from Stanford University. His work has been conferred with the best paper award at ASPLOS, IEEE Micro Top picks and NVIDIA graduate fellowship.