Over the last decade, the advent of high-throughput sequencing techniques brought an exponential growth in sequenced data.
At the same time, the single-thread performance continued to improve by only a few percent point annually.
The growing gap between the performance demand to performance supply became a significant challenge in the path to scientific discovery.
The computational bottleneck of genome analysis pipelines became even more apparent during the ongoing Covid-19 pandemic, where
fast and reliable virus detection and classification tools have been critical for the worldwide genomic surveillance system.
The gap between the performance of a conventional computer architecture and the biological data processing requirements is growing. For example, assembling a human genome from 3rd generation sequenced data may require hundreds of CPU hours. Hence, computational biology and bioinformatics will have to rely on hardware accelerators to allow processing to keep up with the exploding amount of sequenced data.
In a typical application, the dominant portion of the runtime is spent in a small number of computational kernels, making it an excellent target for hardware acceleration. The combination of increasingly large datasets and high performance computing requirements make computational biology a prime candidate to benefit from accelerator architecture research. Potential directions include 3D integration, near-data processing, in-data processing and reconfigurable architectures.
This workshop will focus on architecture and design of hardware accelerators for computational biology and bioinformatics problems. We plan to present and discuss a variety of acceleration techniques, accelerator architectures and their implications on the development of computational biology. This year, we plan to extend the industry angle, by providing a keynote and invited talks from leading industry research specialists.
Bar Ilan University
Short bio: Leonid Yavits is with Bar Ilan University, Israel. He received his MSc and PhD in Electrical Engineering from the Technion. After graduating, he co-founded VisionTech where he co-designed the world’s first single chip MPEG2 codec. Following VisionTech’s acquisition by Broadcom, he managed Broadcom Israel R&D and co-developed a number of video compression products. Later Leonid co-founded Horizon Semiconductors where he co-designed a Set Top Box-on-chip for cable and satellite TV. Leonid’s research interests include non von Neumann computer architectures, processing in memory, and domain specific accelerators. Leonid's research work has earned several awards; among them: IEEE Computer Architecture Letter Journal Best Paper Awards for 2015 and 2017 and best poster award at ICS High Performance Conference 2017.
University of California, San Diego
Short bio: Yatish Turakhia is assistant professor of Electrical and Computer Engineering (ECE) at UCSD. He was previously a postdoctoral scholar at the Genomics Institute at UC Santa Cruz and received his PhD student in from Stanford University. His work has been conferred with the best paper award at ASPLOS, IEEE Micro Top picks and NVIDIA graduate fellowship.